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? 2011 microchip technology inc. ds25048b-page 1 MCP3903 features ? six synchronous sampling 16/24-bit resolution delta-sigma a/d converters with proprietary multi-bit architecture ? 91 db sinad, -100 dbc total harmonic distortion (thd) (up to 35 th harmonic), 102 db spurious-free dynamic range (sfdr) for each channel ? programmable data rate up to 64 ksps ? ultra low-power shutdown mode with <2 a ? -115 db crosstalk between any two channels ? low drift internal voltage reference: 5 ppm/c ? differential voltage reference input pins ? high gain pga on each channel (up to 32 v/v) ? phase delay compensation between each pair of channels with 1 s time resolution ? high-speed addressable 10 mhz spi interface with mode 0,0 and 1,1 compatibility ? independent analog and digital power supplies 4.5v - 5.5v av dd , 2.7v - 3.6v dv dd ? available in small 28-lead ssop package ? extended temperature range: -40c to +125c applications ? energy metering and power measurement ? portable instrumentation ? medical and power monitoring description the MCP3903 is a six-channel analog front end (afe) containing three pairs made out of two synchronous sampling delta-sigma analog-to-digital converters (adc) with pga, a phase delay compensation block, internal voltage reference, and high-speed 10 mhz spi compatible serial interface. the converters contain a proprietary dithering algorithm for reduced idle tones and improved thd. the internal register map contains 24-bit wide adc data words, a modulator output register as well as six 24-bit writable control registers to program gain, over-sampling ratio, phase, resolution, dithering, shut-down, reset and several communication features. the communication is largely simplified with various continuous read modes that can be accessed by the direct memory access (dma) of an mcu and with separate data ready pins that can directly be connected to the interrupt request (irq) input of an mcu. the MCP3903 is capable of interfacing to a large variety of voltage and current sensors including shunts, current transformers, rogowski coils, and hall-effect sensors. package type cs 1 2 3 4 28 27 26 25 24 23 22 21 5 6 7 8 sck dv dd av dd ch0+ ch0- ch1- ch1+ ch2+ 20 9 drb osc1 drc osc2 ch2- ch3- reset 19 10 ch3+ ch4+ sdo sdi 28-lead ssop 18 17 11 12 16 13 refin- dgnd agnd dra ch4- ch5- 15 14 ch5+ refin/out+ six channel delta sigma a/d converter
MCP3903 ds25048b-page 2 ? 2011 microchip technology inc. functional block diagram ch0+ ch0- ch1+ ch1- sdo sdi sck dual ds adc analog digital sinc 3 - + pga xtal oscillator mclk osc1 osc2 dr a reset digital spi interface clock generation sinc 3 - + pga modulator amclk dmclk/drclk dmclk phase shifter phasea <7:0> osr<1:0> pre<1:0> data_ch0<23:0> data_ch1<23:0> cs refin/out+ refin - av dd agnd dgnd dv dd por av dd monitoring modulator v ref + v ref - vrefext voltage reference v ref + - - - ch2+ ch2- ch3+ ch3- dual ds adc sinc 3 - + pga sinc 3 - + pga modulator phase shifter phaseb <7:0> data_ch2<23:0> data_ch3<23:0> modulator - - ch4+ ch4- ch5+ ch5- dual ds adc sinc 3 - + pga sinc 3 - + pga modulator phase shifter phasec <7:0> data_ch4<23:0> data_ch5<23:0> modulator - - dr b dr c por
? 2011 microchip technology inc. ds25048b-page 3 MCP3903 1.0 electrical characteristics the reliability targets section includes the absolute maximum ratings for the device, defining the values that will cause no long term damage regardless of duration. these tables also represent the testing requirements per the max. and min. columns. 1.1 reliability targets absolute maximum ratings ? v dd ................................................................................... 7.0v digital inputs and outputs w.r.t. a gnd ........-0.6v to v dd +0.6v analog input w.r.t. a gnd ..................................... ....-6v to +6v v ref input w.r.t. a gnd ................................-0.6v to v dd +0.6v storage temperature ..................................... -65c to +150c ambient temp. with power applied................ -65c to +125c soldering temperature of leads (10 seconds)............. +300c esd on the analog inputs (hbm,mm)................. 5.0 kv, 500v esd on all other pins (hbm,mm)........................ 5.0 kv, 500v table 1-1: analog specifications target table electrical specifications: unless otherwise indicated, all parameters apply at av dd = 4.5 to 5.5v, dv dd = 2.7 to 3.6v, internal v ref , mclk = 4 mhz;prescale = 1; osr = 64; f s = 1 mhz; f d = 15.625 ksps; t a = -40c to +125c, gain = 1, v in = 1v pp = 353mv rms @ 50/60 hz. param. num. symbol characteristic min. typ. max. units test conditions internal voltage reference a001 v ref voltage -2% 2.35 +2% v vrefext = 0 a002 tc ref tempco ? 5 ? ppm/c vrefext = 0 a003 zout ref output impedance 7 ? k av dd =5v, vrefext = 0 voltage reference input a004 input capacitance ? ? 10 pf a005 v ref differential input voltage range (v ref+ - v ref- ) 2.2 ? 2.6 v v ref = (v ref+ - v ref- ), vrefext = 1 a006 v ref+ absolute voltage on refin+ pin 1.9 ? 2.9 v vrefext = 1 a007 v ref- absolute voltage on refin- pin -0.3 ? +0.3 v v ref- should be connected to agnd when vrefext=0 adc performance a008 resolution (no missing codes) 24 bits osr = 256 (see table 5-2 ) a009 f s sampling frequency see tab l e 4 - 2 khz f s = dmclk = mclk / (4 x prescale) a010 f d output data rate see tab l e 4 - 2 ksps f d = drclk= dmclk / osr = mclk / (4 x prescale x osr) note 1: this specification implies that the adc output is valid over this entire different ial range, i.e. there is no distortion or instability across this input range. dynamic performance is specified at -0.5 db below the maximum signal range, v in = -0.5 dbfs @ 50/60 hz = 333 mv rms , v ref = 2.4v. 2: see terminology section for definition. 3: this parameter is established by characterization and not 100% tested. 4: for these operating currents, the following configurat ion bit settings apply: config register settings: shutdown<5:0> = 000000 , reset<5:0> = 000000 ; vrefext = 0 , clkext = 0 . 5: for these operating currents, the following configurat ion bit settings apply: config register settings: shutdown<5:0> = 111111 , vrefext = 1 , clkext = 1 . 6: applies to all gains. offset error is dependant on pga gain setting. 7: outside of this range, adc accuracy is not specified. an extended input range of +/- 6v can be applied continuously to the part with no risk for damage. 8: for proper operation and to keep adc accuracy, amclk should always be in the range of 1 to 5 mhz with boost bits off. with boost bits on, amclk should be in the range of 1 to 8.192 mhz. amclk = mclk/prescale. when using a crystal, clkext bit should be equal to ? 0 ?.
MCP3903 ds25048b-page 4 ? 2011 microchip technology inc. a011 chn+- analog input absolute voltage -1 +1 v all analog input channels, measured to agnd (note 7) a012 a in analog input leakage current 1na (note 4) a013 (ch n+ - ch n- ) differential input voltage range 500 / gain mv p (note 1) a014 v os offset error -3 3 mv (note 6)(note 2) a015 offset error drift 1 v/c from -40c to 125c a016 ge gain error -3 3 % all gains a017 gain error drift ? 2 ? ppm/c from -40c to 125c a018 inl integral non-linearity 15 ppm gain = 1, dither = on a019 z in input impedance 350 ? ? k proportional to 1/amclk a020 sinad signal-to-noise and distortion ratio 89 91 ? db t = 25c 80 81.5 db a021 thd total harmonic distortion -100 -97 db osr = 256, dither = on; (note 2)(note 3) -90 -87 db a022 snr signal to noise ratio 90 91.5 db t = 25c 80 81.5 db a023 sfdr spurious free dynamic range 102 db osr = 256, dither = on; (note 2) (note 3) 91 db a024 ctalk crosstalk (50 / 60 hz) ? -115 ? db osr = 256, dither = on; (note 2)(note 3) a025 ac psrr ac power supply rejection ? -68 ? db av dd = 5v + 1vpp @ 50 hz a026 dc psrr dc power supply rejection ? -68 ? db av dd = 4.5 to 5.5v, dv dd = 3.3v a027 cmrr dc common mode rejection ratio ?-75 ? dbv cm varies from -1v to +1v; (note 2) oscillator input table 1-1: analog specifications target table (continued) electrical specifications: unless otherwise indicated, all parameters apply at av dd = 4.5 to 5.5v, dv dd = 2.7 to 3.6v, internal v ref , mclk = 4 mhz;prescale = 1; osr = 64; f s = 1 mhz; f d = 15.625 ksps; t a = -40c to +125c, gain = 1, v in = 1v pp = 353mv rms @ 50/60 hz. param. num. symbol characteristic min. typ. max. units test conditions note 1: this specification implies that the adc output is valid over this entire different ial range, i.e. there is no distortion or instability across this input range. dynamic performance is specified at -0.5 db below the maximum signal range, v in = -0.5 dbfs @ 50/60 hz = 333 mv rms , v ref = 2.4v. 2: see terminology section for definition. 3: this parameter is established by characterization and not 100% tested. 4: for these operating currents, the following configurat ion bit settings apply: config register settings: shutdown<5:0> = 000000 , reset<5:0> = 000000 ; vrefext = 0 , clkext = 0 . 5: for these operating currents, the following configurat ion bit settings apply: config register settings: shutdown<5:0> = 111111 , vrefext = 1 , clkext = 1 . 6: applies to all gains. offset error is dependant on pga gain setting. 7: outside of this range, adc accuracy is not specified. an extended input range of +/- 6v can be applied continuously to the part with no risk for damage. 8: for proper operation and to keep adc accuracy, amclk should always be in the range of 1 to 5 mhz with boost bits off. with boost bits on, amclk should be in the range of 1 to 8.192 mhz. amclk = mclk/prescale. when using a crystal, clkext bit should be equal to ? 0 ?.
? 2011 microchip technology inc. ds25048b-page 5 MCP3903 a028 mclk master clock frequency range 1 ? 16.384 mhz (note 8) power specifications p001 av dd operating voltage, analog 4.5 ? 5.5 v p002 dv dd operating voltage, digital 2.7 ? 3.6 v p003 ai dd operating current, analog (note 4) 7.1 9 ma boost bits low on all chan- nels 12.3 16.8 ma boost bits high on all channels p004 di dd operating current, digital ? 1.2 1.7 ma dv dd = 3.6v, mclk = 4mhz ?2.4 3.4 madv dd = 3.6v, mclk = 8.192 mhz p005 i dds,a shutdown current, analog ? ? 1 a -40c to 85c, av dd pin only, (note 5) ?? 3 a -40c to 125c, av dd pin only, (note 5) p006 i dds,d shutdown current, digital ? ? 1 a -40c to 85c, dv dd pin only, (note 5) ?? 5 a -40c to 125c, dv dd pin only, (note 5) table 1-1: analog specifications target table (continued) electrical specifications: unless otherwise indicated, all parameters apply at av dd = 4.5 to 5.5v, dv dd = 2.7 to 3.6v, internal v ref , mclk = 4 mhz;prescale = 1; osr = 64; f s = 1 mhz; f d = 15.625 ksps; t a = -40c to +125c, gain = 1, v in = 1v pp = 353mv rms @ 50/60 hz. param. num. symbol characteristic min. typ. max. units test conditions note 1: this specification implies that the adc output is valid over this entire different ial range, i.e. there is no distortion or instability across this input range. dynamic performance is specified at -0.5 db below the maximum signal range, v in = -0.5 dbfs @ 50/60 hz = 333 mv rms , v ref = 2.4v. 2: see terminology section for definition. 3: this parameter is established by characterization and not 100% tested. 4: for these operating currents, the following configurat ion bit settings apply: config register settings: shutdown<5:0> = 000000 , reset<5:0> = 000000 ; vrefext = 0 , clkext = 0 . 5: for these operating currents, the following configurat ion bit settings apply: config register settings: shutdown<5:0> = 111111 , vrefext = 1 , clkext = 1 . 6: applies to all gains. offset error is dependant on pga gain setting. 7: outside of this range, adc accuracy is not specified. an extended input range of +/- 6v can be applied continuously to the part with no risk for damage. 8: for proper operation and to keep adc accuracy, amclk should always be in the range of 1 to 5 mhz with boost bits off. with boost bits on, amclk should be in the range of 1 to 8.192 mhz. amclk = mclk/prescale. when using a crystal, clkext bit should be equal to ? 0 ?.
MCP3903 ds25048b-page 6 ? 2011 microchip technology inc. 1.2 serial interface characteristics serial interface specifications electrical specifications: unless otherwise indicated, all parameters apply at av dd = 4.5 to 5.5v, dv dd = 2.7 to 3.6v, -40c < t a <+125c, c load = 30 pf. parameters sym min typ max units conditions serial clock frequency f sck ?? 10mhz2.7 dv dd < 3.6 cs setup time t css 50 ? ? ns 2.7 dv dd < 3.6 cs hold time t csh 100 ? ? ns 2.7 dv dd < 3.6 cs disable time t csd 50 ? ? ns ? data setup time t su 10 ? ? ns 2.7 dv dd < 3.6 data hold time t hd 20 ? ? ns 2.7 dv dd < 3.6 serial clock high time t hi 40 ? ? ns 2.7 dv dd < 3.6 serial clock low time t lo 40 ? ? ns 2.7 dv dd < 3.6 serial clock delay time t cld 50 ? ? ns ? serial clock enable time t cle 50 ? ? ns ? output valid from sck low t do ? ? 50 ns 2.7 dv dd < 3.6 output hold time t ho 0??ns output disable time t dis ? ? 50 ns 2.7 dv dd < 3.6 reset pulse width (reset )t mclr 100 ? ? ns 2.7 dv dd < 3.6 data transfer time to dr (data ready) t dodr ?50ns2.7 dv dd < 3.6 data ready pulse low time t drp 1/ dmclk ?s2.7 dv dd < 3.6 schmitt trigger high-level input voltage (all digital inputs) v ih1 .7 dv dd ?dv dd +1 v schmitt trigger low-level input voltage (all digital inputs) v il1 -0.3 ? 0.25 dv dd v hysteresis of schmitt trigger inputs (all digital inputs) v hys 50 ? mv low-level output voltage, sdo pin v ol ? ? 0.4 v sdo pin only, i ol = 2 ma, dv dd = 3.3v low-level output voltage, drn pins v ol 0.4 v dr n pins only, i ol = +1.5 ma, dv dd =3.3v high-level output voltage, sdo pin v oh dv dd - 0.5 ? ? v sdo pin only, i oh = -2 ma, dv dd = 3.3v high-level output voltage, drn pins only v oh dv dd - 0.5 ??vdr n pins only, i oh = -1.5 ma, dv dd =3.3v input leakage current i li ? ? 1 a cs = dv dd , inputs tied to dv dd or dgnd output leakage current i lo ? ? 1 a cs = dv dd , inputs tied to dv dd or dgnd internal capacitance (all inputs and outputs) c int ?? 7 pft a = 25c, sck = 1.0 mhz dv dd = 3.3v (note 1) note 1: this parameter is periodically sampled and not 100% tested.
? 2011 microchip technology inc. ds25048b-page 7 MCP3903 figure 1-1: serial output timing diagram. figure 1-2: serial input timing diagram. temperature characteristics electrical specifications: unless otherwise indicated, all parameters apply at av dd = 4.5 to 5.5v, dv dd = 2.7 to 3.3 v. parameters sym min typ max units conditions temperature ranges operating temperature range t a -40 ? +125 c (note 1) storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 28-lead ssop ja ?71 ? c/w note 1: the internal junction temperature (t j ) must not exceed the absolute maximum specification of +150c. t csh t dis t hi t lo f sck cs sck sdo msb out lsb out don?t care sdi mode 1,1 mode 0,0 t ho t do cs sck sdi lsb in msb in mode 1,1 mode 0,0 t css t su t hd t csd t csh t cld t cle sdo hi-z t hi t lo f sck
MCP3903 ds25048b-page 8 ? 2011 microchip technology inc. h figure 1-3: data ready pulse timing diagram. h figure 1-4: specific timing diagrams. figure 1-5: MCP3903 clock detail. dr sck sdo 1 / drclk t dodr t drp cs v ih timing waveform for t dis hi-z 90% 10% t dis sdo sck sdo t do timing waveform for t do mdat0/1 osc1/clki timing waveform for mdat0/1 modulator output t domdat clkext 1 0 prescale<1:0> 1 / mclk amclk 1 / 4 dmclk 1 / osr drclk osr<1:0> multiplexer clock divider clock divider clock divider crystal oscillator osc1 osc2 prescale f s adc sampling rate f d adc output data rate digital buffer
? 2011 microchip technology inc. ds25048b-page 9 MCP3903 2.0 typical performance curves note: unless otherwise indicated, av dd = 5.0v, dv dd = 3.3 v; internal v ref ; t a = +25c, mclk = 4 mhz; prescale = 1; osr = 64; gain = 1; dithering off; v in = -0.5 dbfs @ 60 hz. . figure 2-1: spectral response. figure 2-2: spectral response. figure 2-3: spectral response. figure 2-4: spectral response. figure 2-5: spectral response. figure 2-6: spectral response. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
MCP3903 ds25048b-page 10 ? 2011 microchip technology inc. note: unless otherwise indicated, av dd = 5.0v, dv dd = 3.3 v; t a = +25c, mclk = 4 mhz; prescale = 1; osr = 64; gain = 1; dithering off; v in = -0.5 dbfs @ 60 hz. . figure 2-7: spectral response. figure 2-8: spurious free dynamic range vs oversampling ratio. figure 2-9: signal-to-noise and distortion vs. oversampling ratio. figure 2-10: signal-to-noise and distortion vs. gain (dithering off). figure 2-11: signal-to-noise and distortion vs. gain (dithering on). figure 2-12: total harmonic distortion vs. oversampling ratio. 120 ic dithering on 80 100 120 d ynamic b ) dithering on dithering off 60 80 100 120 free dynamic n ge (db) dithering on dithering off 40 60 80 100 120 r ious free dynamic range (db) dithering on dithering off 0 20 40 60 80 100 120 spurious free dynamic range (db) dithering on dithering off 0 20 40 60 80 100 120 32 64 128 256 spurious free dynamic range (db) oversampling ratio (osr) dithering on dithering off 0 20 40 60 80 100 120 32 64 128 256 spurious free dynamic range (db) oversampling ratio (osr) dithering on dithering off 120 80 100 120 b ) dithering off dithering on 60 80 100 120 n ad (db) dithering off dithering on 40 60 80 100 120 sinad (db) dithering off dithering on 0 20 40 60 80 100 120 sinad (db) dithering off dithering on 0 20 40 60 80 100 120 32 64 128 256 sinad (db) oversampling ratio (osr) dithering off dithering on 0 20 40 60 80 100 120 32 64 128 256 sinad (db) oversampling ratio (osr) dithering off dithering on 95 100 85 90 95 100 b ) osr = 256 70 75 80 85 90 95 100 n ad (db) osr = 256 osr = 128 osr = 64 60 65 70 75 80 85 90 95 100 sinad (db) osr = 256 osr = 128 osr = 32 osr = 64 50 55 60 65 70 75 80 85 90 95 100 sinad (db) osr = 256 osr = 128 osr = 32 osr = 64 50 55 60 65 70 75 80 85 90 95 100 12481632 sinad (db) gain (v/v) osr = 256 osr = 128 osr = 32 osr = 64 50 55 60 65 70 75 80 85 90 95 100 12481632 sinad (db) gain (v/v) osr = 256 osr = 128 osr = 32 osr = 64 95 100 85 90 95 100 ) osr = 256 75 80 85 90 95 100 a d (db) osr = 256 osr = 128 65 70 75 80 85 90 95 100 sinad (db) osr = 256 osr = 128 osr = 64 55 60 65 70 75 80 85 90 95 100 sinad (db) osr = 256 osr = 128 osr = 64 osr = 32 50 55 60 65 70 75 80 85 90 95 100 12481632 sinad (db) osr = 256 osr = 128 osr = 64 osr = 32 50 55 60 65 70 75 80 85 90 95 100 12481632 sinad (db) gain (v/v) osr = 256 osr = 128 osr = 64 osr = 32
? 2011 microchip technology inc. ds25048b-page 11 MCP3903 note: unless otherwise indicated, av dd = 5.0v, dv dd = 3.3 v; t a = +25c, mclk = 4 mhz; prescale = 1; osr = 64; gain = 1; dithering off; v in = -0.5 dbfs @ 60 hz. . figure 2-13: total harmonic distortion vs. input signal frequency. figure 2-14: total harmonic distortion vs. temperature. figure 2-15: signal-to-noise and distortion vs. input signal frequency. figure 2-16: signal-to-noise and distortion vs. temperature. figure 2-17: signal-to-noise and distortion vs. input signal amplitude. figure 2-18: signal-to-noise and distortion vs. master clock. -60 o n fs=15.625khz osr 64 80 -70 -60 s tortion fs=15.625khz osr=64 -90 -80 -70 -60 o nic distortion d bc) fs=15.625khz osr=64 dithering off -100 -90 -80 -70 -60 h armonic distortion (dbc) fs=15.625khz osr=64 dithering off dithering on -110 -100 -90 -80 -70 -60 t otal harmonic distortion (dbc) fs=15.625khz osr=64 dithering off dithering on -120 -110 -100 -90 -80 -70 -60 20 50 100 200 500 1000 2000 total harmonic distortion (dbc) fs=15.625khz osr=64 dithering off dithering on -120 -110 -100 -90 -80 -70 -60 20 50 100 200 500 1000 2000 total harmonic distortion (dbc) input frequency (hz) fs=15.625khz osr=64 dithering off dithering on 0 on fs=15.625khz - 40 -20 0 d istortion fs=15.625khz osr=64 -60 -40 -20 0 m onic distortion ( dbc) fs=15.625khz osr=64 -80 -60 -40 -20 0 harmonic distortion (dbc) fs=15.625khz osr=64 - 120 -100 -80 -60 -40 -20 0 total harmonic distortion (dbc) fs=15.625khz osr=64 -120 -100 -80 -60 -40 -20 0 -40 -20 0 25 45 85 105 125 total harmonic distortion (dbc) temperature ( c) fs=15.625khz osr=64 -120 -100 -80 -60 -40 -20 0 -40 -20 0 25 45 85 105 125 total harmonic distortion (dbc) temperature (c) fs=15.625khz osr=64 90 100 dithering off 70 80 90 100 b ) dithering off dithering on 40 50 60 70 80 90 100 n ad (db) dithering off dithering on 20 30 40 50 60 70 80 90 100 sinad (db) dithering off dithering on fs = 15 625khz 0 10 20 30 40 50 60 70 80 90 100 sinad (db) dithering off dithering on fs=15.625khz osr=64 0 10 20 30 40 50 60 70 80 90 100 20 50 100 200 500 1000 2000 sinad (db) input frequency (hz) dithering off dithering on fs=15.625khz osr=64 0 10 20 30 40 50 60 70 80 90 100 20 50 100 200 500 1000 2000 sinad (db) input frequency (hz) dithering off dithering on fs=15.625khz osr=64 120 fs=15.625khz 80 100 120 ) fs=15.625khz osr=64 60 80 100 120 a d (db) fs=15.625khz osr=64 40 60 80 100 120 sinad (db) fs=15.625khz osr=64 20 40 60 80 100 120 sinad (db) fs=15.625khz osr=64 0 20 40 60 80 100 120 -40 -20 0 25 45 85 105 125 sinad (db) fs=15.625khz osr=64 0 20 40 60 80 100 120 -40 -20 0 25 45 85 105 125 sinad (db) temperature (c) fs=15.625khz osr=64 80 90 60 70 80 90 b) 40 50 60 70 80 90 n ad (db) 20 30 40 50 60 70 80 90 sinad (db) 0 10 20 30 40 50 60 70 80 90 sinad (db) -10 0 10 20 30 40 50 60 70 80 90 0.00001 0.001 0.1 10 1000 sinad (db) input signal amplitude (mv) -10 0 10 20 30 40 50 60 70 80 90 0.00001 0.001 0.1 10 1000 sinad (db) input signal amplitude (mv)
MCP3903 ds25048b-page 12 ? 2011 microchip technology inc. note: unless otherwise indicated, av dd = 5.0v, dv dd = 3.3 v; t a = +25c, mclk = 4 mhz; prescale = 1; osr = 64; gain = 1; dithering off; v in = -0.5 dbfs @ 60 hz. figure 2-19: offset error vs. temperature (channel 0). figure 2-20: channel-to-channel offset match vs. temperature. figure 2-21: gain error vs. temperature. figure 2-22: internal voltage reference vs. temperature. figure 2-23: internal voltage reference vs. supply voltage. figure 2-24: noise histogram. 120 1.40 g=8 0.80 1.00 1.20 1.40 (mv) g=16 g=1 g=8 0.40 0.60 0.80 1.00 1.20 1.40 error (mv) g=2 g=16 g=1 g=8 000 0.20 0.40 0.60 0.80 1.00 1.20 1.40 o ffset error (mv) g=4 g=2 g=16 g=1 g=8 - 0.40 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 offset error (mv) g=32 g=4 g=2 g=16 g=1 g=8 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 -40 -20 0 25 45 85 105 125 offset error (mv) temperature ( c) g=32 g=4 g=2 g=16 g=1 g=8 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 -40 -20 0 25 45 85 105 125 offset error (mv) temperature (c) g=32 g=4 g=2 g=16 g=1 g=8 140 1.60 ch1 ch3 100 1.20 1.40 1.60 r (mv) ch1 ch3 060 0.80 1.00 1.20 1.40 1.60 t error (mv) ch0 ch1 ch2 ch3 ch5 0.40 0.60 0.80 1.00 1.20 1.40 1.60 o ffset error (mv) ch0 ch1 ch2 ch3 ch4 ch5 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 offset error (mv) ch0 ch1 ch2 ch3 ch4 ch5 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 -40 -20 0 25 45 85 105 125 offset error (mv) temperature (c) ch0 ch1 ch2 ch3 ch4 ch5 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 -40 -20 0 25 45 85 105 125 offset error (mv) temperature (c) ch0 ch1 ch2 ch3 ch4 ch5 0.00 - 0.10 -0.05 0.00 ( %) g=1 g=8 -0.15 -0.10 -0.05 0.00 error (%) g=32 g=16 g=2 g=1 g=8 -0.20 -0.15 -0.10 -0.05 0.00 gain error (%) g=32 g=16 g=2 g=1 g=8 030 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 gain error (%) g=32 g=4 g=16 g=2 g=1 g=8 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 -40 -20 0 25 45 85 105 125 gain error (%) temperature ( c) g=32 g=4 g=16 g=2 g=1 g=8 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 -40 -20 0 25 45 85 105 125 gain error (%) temperature (c) g=32 g=4 g=16 g=2 g=1 g=8 2.360 ( v) 2.355 2.360 rence (v) 2.350 2.355 2.360 e reference (v) 2.345 2.350 2.355 2.360 vo ltage reference (v) 2.340 2.345 2.350 2.355 2.360 int. voltage reference (v) 2.340 2.345 2.350 2.355 2.360 -40 -20 0 25 45 85 105 125 int. voltage reference (v) temperature ( c) 2.340 2.345 2.350 2.355 2.360 -40 -20 0 25 45 85 105 125 int. voltage reference (v) temperature (c) 2 35472 2.35473 2.35471 2.35472 2.35473 n ce (v) 2 35469 2.35470 2.35471 2.35472 2.35473 r eference (v) 2.35468 2.35469 2.35470 2.35471 2.35472 2.35473 a ge reference (v) 2 35466 2.35467 2.35468 2.35469 2.35470 2.35471 2.35472 2.35473 n t. voltage reference (v) 2.35466 2.35467 2.35468 2.35469 2.35470 2.35471 2.35472 2.35473 4.5 5 5.5 int. voltage reference (v) power supply (v) 2.35466 2.35467 2.35468 2.35469 2.35470 2.35471 2.35472 2.35473 4.5 5 5.5 int. voltage reference (v) power supply (v)
? 2011 microchip technology inc. ds25048b-page 13 MCP3903 note: unless otherwise indicated, av dd = 5.0v, dv dd = 3.3 v; t a = +25c, mclk = 4 mhz; prescale = 1; osr = 64; gain = 1; dithering off; v in = -0.5 dbfs @ 60 hz. figure 2-25: integral non-linearity (dithering off). figure 2-26: integral non-linearity (dithering on). figure 2-27: operating current vs. master clock (mclk). 40 50 ch0 20 30 40 50 m ) ch0 10 0 10 20 30 40 50 l (ppm) ch0 ch1 30 -20 -10 0 10 20 30 40 50 inl (ppm) ch0 ch1 -50 -40 -30 -20 -10 0 10 20 30 40 50 inl (ppm) ch0 ch1 -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.5 -0.25 0 0.25 0.5 inl (ppm) input voltage (v) ch0 ch1 -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.5 -0.25 0 0.25 0.5 inl (ppm) input voltage (v) ch0 ch1 40 50 20 30 40 50 ch0 10 0 10 20 30 40 50 ( ppm) ch0 ch1 30 -20 -10 0 10 20 30 40 50 inl (ppm) ch0 ch1 - 50 -40 -30 -20 -10 0 10 20 30 40 50 inl (ppm) ch0 ch1 -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.5 -0.25 0 0.25 0.5 inl (ppm) input voltage (v) ch0 ch1 -50 -40 -30 -20 -10 0 10 20 30 40 50 -0.5 -0.25 0 0.25 0.5 inl (ppm) input voltage (v) ch0 ch1 8 9 6 7 8 9 ) aidd boost off 4 5 6 7 8 9 d (ma) aidd boost off 2 3 4 5 6 7 8 9 idd (ma) aidd boost off 0 1 2 3 4 5 6 7 8 9 idd (ma) aidd boost off didd 0 1 2 3 4 5 6 7 8 9 1234 idd (ma) mclk frequency(mhz) aidd boost off didd 0 1 2 3 4 5 6 7 8 9 1234 idd (ma) mclk frequency(mhz) aidd boost off didd
MCP3903 ds25048b-page 14 ? 2011 microchip technology inc. 3.0 pin description table 3-1: pin function table 3.1 reset this pin is active low and places the entire chip in a reset state when active. when reset = 0 , all registers are reset to their default value, no communication can take place, no clock is distributed inside the part. this state is equivalent to a por state. since the default state of the adcs is on, the analog power consumption when reset = 0 is equivalent to when reset = 1 . only the digital power consumption is largely reduced because this current consumption is essentially dynamic and is reduced drastically when there is no clock running. all the analog biases are enabled during a reset so that the part is fully operational just after a reset rising edge. this input is schmitt triggered. 3.2 digital v dd (dv dd ) dv dd is the power supply pin for the digital circuitry within the MCP3903. this pin requires appropriate bypass capacitors and should be maintained between 2.7v and 3.6v for specified operation. pin no. symbol function 1av dd analog power supply pin 2 ch0+ non-inverting analog input pin for channel 0 3 ch0- inverting analog input pin for channel 0 4 ch1- inverting analog input pin for channel 1 5 ch1+ non-inverting analog input pin for channel 1 6 ch2+ non-inverting analog input pin for channel 2 7 ch2- inverting analog input pin for channel 2 8 ch3- inverting analog input pin for channel 3 9 ch3+ non-inverting analog input pin for channel 3 10 ch4+ non-inverting analog input pin for channel 4 11 ch4- inverting analog input pin for channel 4 12 ch5- inverting analog input pin for channel 5 13 ch5+ non-inverting analog input pin for channel 5 14 refin+/out non-inverting voltage reference input and internal reference output pin 15 refin- inverting voltage reference input pin 16 a gnd analog ground pin, return path for internal analog circuitry 17 d gnd digital ground pin, return path for internal digital circuitry 18 dr a data ready signal output for channels pair a 19 dr b data ready signal output for channels pair b 20 dr c data ready signal output for channels pair c 21 osc1 oscillator crystal connection pin or clock input pin 22 osc2 oscillator crystal connection pin 23 cs chip select for serial interface 24 sck serial interface clock pin 25 sdo serial interface data output pin 26 sdi serial interface data input pin 27 reset master reset logic input pin 28 dv dd digital power supply pin
? 2011 microchip technology inc. ds25048b-page 15 MCP3903 3.3 analog v dd (av dd ) av dd is the power supply pin for the analog circuitry within the MCP3903. this pin requires appropriate bypass capacitors and should be maintained to 5v 10% for specified operation. 3.4 adc differential analog inputs(chn+/chn-) chn- and chn+, are the two fully-differential analog voltage inputs for the delta-sigma adcs. there are six channels in total grouped in three channel pairs. the linear and specified region of the channels are dependent on the pga gain. this region corresponds to a differential voltage range of 500 mv/gain with v ref = 2.4v. the maximum absolute voltage, with respect to agnd, for each chn+/- input pin is +/-1v with no distortion and 6v with no breaking after continuous voltage. 3.5 analog ground (agnd) agnd is the ground connection to internal analog circuitry (adcs, pga, voltage reference, por). to ensure accuracy and noise cancellation, this pin must be connected to the same ground as dgnd, preferably with a star connection. if an analog ground plane is available, it is recommended that this pin be tied to this plane of the pcb. this plane should also reference all other analog circuitry in the system. 3.6 non-inverting reference input, internal reference output (refin+/out) this pin is the non-inverting side of the differential voltage reference input for all adcs or the internal voltage reference output. when vrefext = 1 , and an external voltage reference source can be used, the internal voltage reference is disabled. when using an external differential voltage reference, it should be connected to its v ref+ pin. when using an external single-ended reference, it should be connected to this pin. when vrefext = 0 , the internal voltage reference is enabled and connected to this pin through a switch. this voltage reference has minimal drive capability and thus needs proper buffering and bypass capacitances (10 f tantalum in parallel with 0.1 f ceramic) if used as a voltage source. for optimal performance, bypass capacitances should be connected between this pin and agnd at all times even when the internal voltage reference is used. 3.7 inverting reference input (refin-) this pin is the inverting side of the differential voltage reference input for both adcs. when using an external differential voltage reference, it should be connected to its v ref- pin. when using an external single-ended voltage reference, or when vrefext = 0 (default) and using the internal voltage reference, this pin should be directly connected to agnd. 3.8 digital ground connection (dgnd) dgnd is the ground connection to internal digital circuitry (sinc filters, oscillator, serial interface). to ensure accuracy and noise cancellation, dgnd must be connected to the same ground as agnd, preferably with a star connection. if a digital ground plane is available, it is recommended that this pin be tied to this plane of the printed circuit board (pcb). this plane should also reference all other digital circuitry in the system. 3.9 dr n (data ready pins) the data ready pins indicate if a new conversion result is ready to be read on each of the a, b and c pairs of adcs. the default state of this pin is high when dr_hizn=1 and is high impedance when dr_hizn=0 (default). after each conversion is finished, a low pulse will take place on the data ready pins to indicate the conversion result is ready as an interrupt. this pulse is synchronous with the master clock and has a defined and constant width. the data ready pins are independent of the spi interface and act like an interrupt output.the data ready pins state is not latched and the pulse width (and period) are both determined by the mclk frequency, over-sampling rate, and internal clock pre- scale settings. the dr pulse width is equal to one dmclk period and the frequency of the pulses is equal to drclk (see figure 1-3 ). note: these pins should not be left floating when dr_hiz bit is low; a 100k ? pull-up resistor connected to dv dd is recom- mended.
MCP3903 ds25048b-page 16 ? 2011 microchip technology inc. 3.10 oscillator and master clock input pins (osc1/clki, osc2) osc1/clki and osc2 provide the master clock for the device. when clkext = 0 (default), a resonant crystal or clock source with a similar sinusoidal waveform must be placed across these pins to ensure proper operation. the typical clock frequency specified is 4 mhz. however, the clock frequency can be 1 mhz to 5 mhz without disturbing adc accuracy. with the current boost circuit enabled, the master clock can be used up to 8.192 mhz without disturbing adc accuracy. appropriate load capacitance should be connected to these pins for proper operation. 3.11 cs (chip select) this pin is the spi chip select that enables the serial communication. when this pin is high, no communication can take place. a chip select falling edge initiates the serial communication and a chip select rising edge terminates the communication. no communication can take place even when cs is low and when reset is low. this input is schmitt-triggered. 3.12 sck (serial data clock) this is the serial clock pin for spi communication. data is clocked into the device on the rising edge of sck. data is clocked out of the device on the falling edge of sck. the MCP3903 interface is compatible with both spi 0,0 and 1,1 modes. the maximum clock speed specified is 10 mhz. this input is schmitt triggered. 3.13 sdo (serial data output) this is the spi data output pin. data is clocked out of the device on the falling edge of sck. this pin stays at high impedance during the control byte. it also stays at high impedance during the whole communication for write commands and when the cs pin is high or when the reset pin is low. this pin is active only when a read command is processed. each read is processed by a packet of 24 bits (size of each register), except on the adc output registers when width=0. 3.14 sdi (serial data input) this is the spi data input pin. data is clocked into the device on the rising edge of sck. when cs is low, this pin is used to communicate with a series of 8-bit commands. the interface is half-duplex (inputs and outputs do not happen at the same time). each communication starts with a chip select falling edge followed by an 8-bit control byte entered through the sdi pin. each write is processed by packets of 24 bits (size of each register). each command is either a read or a write command. toggling sdi during a read command has no effect. this input is schmitt-triggered. note: when clkext = 1 , the crystal oscillator is disabled, as well as the osc2 input. the osc1 becomes the master clock input clki, direct path for an external clock source, for example a clock source generated by an mcu.
? 2011 microchip technology inc. ds25048b-page 17 MCP3903 4.0 terminology and formulas this section defines the terms and formulas used throughout this data sheet. the following terms are defined: mclk - master clock amclk - analog master clock dmclk - digital master clock drclk - data rate clock osr - oversampling ratio offset error gain error integral non-linearity error signal-to-noise ratio (snr) signal-to-noise ratio and distortion (sinad) total harmonic distortion (thd) spurious-free dynamic range (sfdr) MCP3903 delta-sigma architecture idle tones dithering crosstalk psrr cmrr adc reset mode hard reset mode (reset = 0) adc shutdown mode full shutdown mode 4.1 mclk - master clock this is the fastest clock present in the device. this is the frequency of the crystal placed at the osc1/osc2 inputs when clkext = 0 or the frequency of the clock input at the osc1/clki when clkext = 1 . 4.2 amclk - analog master clock this is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the config prescale<1:0> register bits. the analog portion includes the pgas and the two sigma-delta modulators. equation 4-1: 4.3 dmclk - digital master clock this is the clock frequency that is present on the digital portion of the device, after prescaling and division by 4. this is also the sampling frequency, that is the rate at which the modulator outputs are refreshed. each period of this clock corresponds to one sample and one modulator output. equation 4-2: 4.4 drclk - data rate clock this is the output data rate i.e. the rate at which the adcs output new data. each new data is signaled by a data ready pulse on the dr pin. this data rate is depending on the osr and the prescaler with the following formula: equation 4-3: table 4-1: MCP3903 oversampling ratio settings config analog master clock prescale pre<1:0> 00 amclk = mclk/ 1 (default) 01 amclk = mclk/ 2 10 amclk = mclk/ 4 11 amclk = mclk/ 8 amclk mclk prescale ------------------------------ - = dmclk amclk 4 -------------------- - mclk 4 prescale --------------------------------------- - == drclk dmclk osr ---------------------- amclk 4osr --------------------- mclk 4 osr prescale ---------------------------------------------------------- - ===
MCP3903 ds25048b-page 18 ? 2011 microchip technology inc. since this is the output data rate, and since the decimation filter is a sinc (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. the following table describes the various combinations of osr and prescale and their associated amclk, dmclk and drclk rates. 4.5 osr - oversampling ratio the ratio of the sampling frequency to the output data rate is osr = dmclk/drclk. the default osr is 64, or with mclk = 4 mhz, prescale = 1 , amclk = 4 mhz, f s = 1 mhz, f d = 15.625 ksps. the following bits in the config1 register are used to change the oversampling ratio (osr). 4.6 offset error this is the error induced by the adc when the inputs are shorted together (v in = 0v). the specification incorporates both pga and adc offset contributions. this error varies with pga and osr settings. the offset is different on each channel and varies from chip to chip. this offset error can easily be calibrated out by a mcu with a subtraction. the offset is specified in mv. the offset on the MCP3903 has a low temperature coefficient, see section 2.0 ?typical performance curves? . 4.7 gain error this is the error induced by the adc on the slope of the transfer function. it is the deviation expressed in % compared to the ideal transfer function defined by equation 5-3 . the specification incorporates both pga and adc gain error contributions, but not the v ref contribution (it is measured with an external v ref ).this error varies with pga and osr settings. the gain error on the MCP3903 has a low temperature coefficient. see the typical performance curves for more information. table 4-2: device data rates in f unction of mclk, osr, and prescale pre <1:0> osr <1:0> osr amclk dmclk drclk drclk (ksps) 1 1 1 1 256 mclk/8 mclk/32 mclk/8192 0.4882 1 1 1 0 128 mclk/8 mclk/32 mclk/4096 0.976 1 1 0 1 64 mclk/8 mclk/32 mclk/2048 1.95 1 1 0 0 32 mclk/8 mclk/32 mclk/1024 3.9 1 0 1 1 256 mclk/4 mclk/16 mclk/4096 0.976 1 0 1 0 128 mclk/4 mclk/16 mclk/2048 1.95 1 0 0 1 64 mclk/4 mclk/16 mclk/1024 3.9 1 0 0 0 32 mclk/4 mclk/16 mclk/512 7.8125 0 1 1 1 256 mclk/2 mclk/8 mclk/2048 1.95 0 1 1 0 128 mclk/2 mclk/8 mclk/1024 3.9 0 1 0 1 64 mclk/2 mclk/8 mclk/512 7.8125 0 1 0 0 32 mclk/2 mclk/8 mclk/256 15.625 0 0 1 1 256 mclk mclk/4 mclk/1024 3.9 0 0 1 0 128 mclk mclk/4 mclk/512 7.8125 000164 mclk mclk/4 mclk/256 15.625 0 0 0 0 32 mclk mclk/4 mclk/128 31.25 note: for osr = 32 and 64, dither = 0 . for osr = 128 and 256, dither = 1 . table 4-3: MCP3903 oversampling ratio settings config over sampling ratio (osr) osr<1:0> 00 32 01 64 (default) 10 128 11 256
? 2011 microchip technology inc. ds25048b-page 19 MCP3903 4.8 integral non-linearity error integral non-linearity error is the maximum deviation of an adc transition point from the corresponding point of an ideal transfer function, with the offset and gain errors removed, or with the end points equal to zero. it is the maximum remaining error after calibration of offset and gain errors for a dc input signal. 4.9 signal-to-noise ratio (snr) for the MCP3903 adc, the signal-to-noise ratio is a ratio of the output fundamental signal power to the noise power (not including the harmonics of the signal), when the input is a sinewave at a predetermined frequency. it is measured in db. usually, only the maximum signal to noise ratio is specified. the snr figure depends mainly on the osr and dither settings of the device. equation 4-4: signal-to-noise ratio 4.10 signal-to-noise ratio and distortion (sinad) the most important figure of merit for the analog performance of the adcs present on the MCP3903 is the signal-to-noise and distortion (sinad) specification. signal-to-noise and distortion ratio is similar to signal- to-noise ratio, with the exception that you must include the harmonics power in the noise power calculation. the sinad specification depends mainly on the osr and dither settings. equation 4-5: sinad equation the calculated combination of snr and thd per the following formula also yields sinad: equation 4-6: sinad, thd, and snr relationship 4.11 total harmonic distortion (thd) the total harmonic distortion is the ratio of the output harmonics power to the fundamental signal power for a sinewave input and is defined by the following equation. equation 4-7: the thd calculation includes the first 35 harmonics for the MCP3903 specifications. the thd is usually only measured with respect to the 10 first harmonics. thd is sometimes expressed in %. for converting the thd in %, here is the formula: equation 4-8: this specification depends mainly on the dither setting. 4.12 spurious-free dynamic range (sfdr) sfdr is the ratio between the output power of the fundamental and the highest spur in the frequency spectrum. the spur frequency is not necessarily a harmonic of the fundamental even though it is usually the case. this figure represents the dynamic range of the adc when a full-scale signal is used at the input. this specification depends mainly on the dither setting. equation 4-9: snr db () 10 signalpower noisepower ---------------------------------- ?? ?? log = sinad db () 10 signalpower noise harmonicspower + ------------------------------------------------------------------- - ?? ?? log = sinad db () 10 10 snr 10 ----------- ?? ?? 10 thd ? 10 --------------- - ?? ?? + log = thd db () 10 harmonicspower fundamentalpower ---------------------------------------------------- - ?? ?? log = thd % () 100 10 thd db () 20 ------------------------ = sfdr db () 10 fundamentalpower highestspurpower ---------------------------------------------------- - ?? ?? log =
MCP3903 ds25048b-page 20 ? 2011 microchip technology inc. 4.13 MCP3903 delta-sigma architecture the MCP3903 incorporates six delta-sigma adcs with a multi-bit digital to analog converter as quantizer. a delta-sigma adc is an oversampling converter that incorporates a built-in modulator which is digitizing the quantity of charge integrated by the modulator loop (see figure 5-1 ). the quantizer is the block that is per- forming the analog-to-digital conversion. the quantizer is typically 1-bit, or a simple comparator which helps to maintain the linearity performance of the adc (the dac structure is inherently linear in this case). multi-bit quantizers help to lower the quantization error (the error fed back in the loop can be very large with 1-bit quantizers) without changing the order of the modulator or the osr, which leads to better snr figures. however, typically, the linearity of such architectures is more difficult to achieve since the dac is no more simple to realize and its linearity limits the thd of such adcs. the MCP3903?s 5-level quantizer is a flash adc composed of 4 comparators arranged with equally spaced thresholds and a thermometer coding. the MCP3903 also includes proprietary 5-level dac architecture that is inherently linear for improved thd figures. 4.14 idle tones a delta-sigma converter is an integrating converter. it also has a finite quantization step (lsb) which can be detected by its quantizer. a dc input voltage that is below the quantization step should only provide an all zeros result since the input is not large enough to be detected. as an integrating device, any delta-sigma will show, in this case, idle tones. this means that the output will have spurs in the frequency content that are depending on the ratio between quantization step voltage and the input voltage. these spurs are the result of the integrated sub-quantization step inputs that will eventually cross the quantization steps after a long enough integration. this will induce an ac frequency at the output of the adc and can be shown in the adc output spectrum. these idle tones are residues that are inherent to the quantization process and the fact that the converter is integrating at all times without being reset. they are residues of the finite resolution of the conversion process. they are very difficult to attenuate and they are heavily signal dependent. they can degrade both sfdr and thd of the converter, even for dc inputs. they can be localized in the baseband of the converter and thus difficult to filter from the actual input signal. for power metering applications, idle tones can be very disturbing because energy can be detected even at the 50 or 60 hz frequency, depending on the dc offset of the adcs, while no power is really present at the inputs. the only practical way to suppress or attenuate idle tones phenomenon is to apply dithering to the adc. the idle tones amplitudes are a function of the order of the modulator, the osr and the number of levels in the quantizer of the modulator. a higher order, a higher osr, or a higher number of levels for the quantizer will attenuate the idle tones amplitude. 4.15 dithering in order to suppress or attenuate the idle tones present in any delta-sigma adcs, dithering can be applied to the adc. dithering is the process of adding an error to the adc feedback loop in order to ?decorrelate? the outputs and ?break? the idle tone?s behavior. usually a random or pseudo-random generator adds an analog or digital error to the feedback loop of the delta-sigma adc in order to ensure that no tonal behavior can happen at its outputs. this error is filter by the feedback loop and typically has a zero average value so that the converter static transfer function is not disturbed by the dithering process. however, the dithering process slightly increases the noise floor (it adds noise to the part) while reducing its tonal behavior and thus improving sfdr and thd. the dithering process scrambles the idle tones into baseband white noise and ensures that dynamic specs (snr, sinad, thd, sfdr) are less signal dependent. the MCP3903 incorporates a proprietary dithering algorithm on all adcs in order to remove idle tones and improve thd, which is crucial for power metering applications.
? 2011 microchip technology inc. ds25048b-page 21 MCP3903 4.16 crosstalk the crosstalk is defined as the perturbation caused by one adc channel on the other adc channel. it is a measurement of the isolation between the six adcs present in the chip. this measurement is a two-step procedure: 1. measure one adc input with no perturbation on any other adc (adc inputs shorted). 2. measure the same adc input with a perturbation sine wave signal on the other adc at a certain predefined frequency. the crosstalk is then the ratio between the output power of the adc when the perturbation is present and when it is not divided by the power of the perturbation signal. a lower crosstalk value implies more independence and isolation between the six channels. the measurement of this signal is performed under the following conditions: ?gain = 1 , ? prescale = 1 , ? osr = 256, ? mclk = 4 mhz step 1 ? ch0+=ch0-=agnd ? chn+=chn-=agnd, n different than 0 step 2 ? ch0+=ch0-=agnd ? chn+ - chn-=1v p-p @ 50/60 hz (full-scale sine wave) the crosstalk is then calculated with the following formula: equation 4-10: 4.17 psrr this is the ratio between a change in the power supply voltage and the adc output codes. it measures the influence of the power supply voltage on the adc outputs. the psrr specification can be dc (the power supply is taking multiple dc values) or ac (the power supply is a sinewave at a certain frequency with a certain common mode). in ac, the amplitude of the sinewave is representing the change in the power supply. it is defined as: equation 4-11: where v out is the equivalent input voltage that the output code translates to with the adc transfer function. in the MCP3903 specification, av dd varies from 4.5v to 5.5v, and for ac psrr a 50/60 hz sinewave is chosen, centered around 5v with a maximum 500 mv amplitude. the psrr specification is measured with dv dd = 3.3v. 4.18 cmrr this is the ratio between a change in the common-mode input voltage and the adc output codes. it measures the influence of the common-mode input voltage on the adc outputs. the cmrr specification can be dc (the common-mode input voltage is taking multiple dc values) or ac (the common-mode input voltage is a sinewave at a certain frequency with a certain common mode). in ac, the amplitude of the sinewave is representing the change in the power supply. it is defined as: equation 4-12: where v cm = (chn+ + chn-)/2 is the common-mode input voltage and v out is the equivalent input voltage that the output code translates to with the adc transfer function. in the MCP3903 specification, vcm varies from -1v to +1v, and for ac specification a 50/60 hz sinewave is chosen centered around 0v with a 500 mv amplitude. 4.19 adc reset mode adc reset mode (called also soft reset mode) can only be entered through setting high the reset<5:0> bits in the configuration register. this mode is defined as the condition where the converters are active but their output is forced to 0. the registers are not affected in this reset mode and retain their values. the adcs can immediately output meaningful codes after leaving reset mode (and after the sinc filter settling time of 3/drclk). this mode is both entered and exited through setting of bits in the configuration register. each converter can be placed in soft reset mode independently. the configuration registers are not modified by the soft reset mode. ctalk db () 10 ch0power chnpower -------------------------------- - ?? ?? log = psrr db () 20 v out av dd ------------------ - ?? ?? log = cmrr db () 20 v out v cm ----------------- ?? ?? log =
MCP3903 ds25048b-page 22 ? 2011 microchip technology inc. a data ready pulse will not be generated by any adc while in reset mode. when an adc exists adc reset mode, any phase delay present before reset was entered will still be present. if one adc was not in reset, the adc leaving reset mode will automatically resynchronize the phase delay relative to the other adc channel, per the phase delay register block and give data ready pulses accord- ingly. if an adc is placed in reset mode while the other is converting, it is not shutting down the internal clock. when going back out of reset, it will be resynchronized automatically with the clock that did not stop during reset. if all adcs are in soft reset or shutdown modes, the clock is no longer distributed to the digital core for low power operation. once the adc is back to normal operation, the clock is automatically distributed again. 4.20 hard reset mode (reset = 0) this mode is only available during a por or when the reset pin is pulled low. the reset pin low state places the device in a hard reset mode. in this mode, all internal registers are reset to their default state. the dc biases for the analog blocks are still active, i.e. the MCP3903 is ready to convert. however, this pin clears all conversion data in the adcs. the comparator outputs of all adcs are forced to their reset state ( 0011 ). the sinc filters are all reset, as well as their double output buffers. see serial timing for minimum pulse low time, in section 1.0 ?electrical characteristics? . during a hard reset, no communication with the part is possible. the digital interface is maintained in a reset state. 4.21 adc shutdown mode adc shutdown mode is defined as a state where the converters and their biases are off, consuming only leakage current. after this is removed, start-up delay time (sinc filter settling time) will occur before outputting meaningful codes. the start-up delay is needed to power-up all dc biases in the channel that was in shutdown. this delay is the same than t por and any dr pulse coming within this delay should be discarded. each converter can be placed in shutdown mode independently. the config registers are not modified by the shutdown mode. this mode is only available through programming of the shutdown<5:0> bits in the config register. the output data is flushed to all zeros while in adc shutdown. no data ready pulses are generated by any adc while in adc shutdown mode. when an adc exits adc shutdown mode, any phase delay present before shutdown was entered will still be present. if one adc was not in shutdown, the adc leaving shutdown mode will automatically resynchro- nize the phase delay relative to the other adc channel, per the phase delay register block and give data ready pulses accordingly. if an adc is placed in shutdown while others are con- verting, then the internal clock will not shut down. when going back out of shutdown, it will be automatically resynchronized with the clock that did not stop during reset. if all adcs are in adc reset or adc shutdown modes, the clock is not distributed to the digital core for low power operation. once any of the adc is back to nor- mal operation, the clock is automatically distributed again. 4.22 full shutdown mode the lowest power consumption can be achieved when shutdown<5:0>= 111111 , vrefext=clkext= 1 . this mode is called ?full shutdown mode?, and no analog circuitry is enabled. in this mode, the por a vdd monitoring circuit is also disabled. when the clock is idle (osc1 = high or low continuously), no clock is propagated throughout the chip. all adcs are in shutdown, the internal voltage reference is disabled and the internal oscillator is disabled. the only circuit that remains active is the spi interface but this circuit does not induce any static power consumption. if sck is idle, the only current consumption comes from the leakage currents induced by the transistors and is less than 1 a on each power supply, for temperatures lower than 85c. this mode can be used to power down the chip completely and avoid power consumption when there is no data to convert at the analog inputs. any sck or mclk edge coming while in this mode will induce dynamic power consumption. once any of the shutdown, clkext and vrefext bits returns to 0 , the por av dd monitoring block is back to operation and av dd monitoring can take place.
? 2011 microchip technology inc. ds25048b-page 23 MCP3903 5.0 device overview 5.1 analog inputs (chn+/-) the MCP3903 analog inputs can be connected directly to current and voltage transducers (such as shunts, current transformers, or rogowski coils). each input pin is protected by specialized esd structures that are certified to pass 5 kv hbm and 500v mm contact charge. these structures allow bipolar 6v continuous voltage with respect to agnd, to be present at their inputs without the risk of permanent damage. all channels have fully differential voltage inputs for better noise performance. the absolute voltage at each pin relative to agnd should be maintained in the 1v range during operation in order to ensure the specified adc accuracy. the common-mode signals should be adapted to respect both the previous conditions and the differential input voltage range. for best performance, the common-mode signals should be maintained to agnd. 5.2 programmable gain amplifiers (pga) the six programmable gain amplifiers (pgas) reside at the front-end of each delta-sigma adc. they have two functions: translate the common-mode of the input from agnd to an internal level between agnd and a vdd , and amplify the input differential signal. the translation of the common mode does not change the differential signal but recenters the common-mode so that the input signal can be properly amplified. the pga block can be used to amplify very low signals, but the differential input range of the delta-sigma modulator must not be exceeded. the pga is controlled by the pga_chn<2:0> bits in the gain register. the following table represents the gain settings for the pga: 5.3 delta-sigma modulator 5.3.1 architecture all adcs are identical in the MCP3903 and they include a second-order modulator with a multi-bit dac architecture (see figure 5-1 ). the quantizer is a flash adc composed of 4 comparators with equally spaced thresholds and a thermometer output coding. the proprietary 5-level architecture ensures minimum quantization noise at the outputs of the modulators without disturbing linearity or inducing additional distortion. the sampling frequency is dmclk (typically 1 mhz with mclk=4 mhz) so the modulator outputs are refreshed at a dmclk rate. the modulator outputs are available in the mod register. each modulator also includes a dithering algorithm that can be enabled through the dither<5:0> bits in the configuration register. this dithering process improves thd and sfdr (for high osr settings) while increasing slightly the noise floor of the adcs. for power metering applications and applications that are distortion-sensitive, it is recommended to keep dither enabled for all adcs. in the case of power metering applications, thd and sfdr are critical specifications to optimize snr (noise floor). this is not really problematic due to large averaging factor at the output of the adcs, therefore even for low osr settings, the dithering algorithm will show a positive impact on the performance of the application. figure 5-1 represents a simplified block diagram of the delta-sigma adc present on MCP3903. figure 5-1: simplified delta-sigma adc block diagram. table 5-1: pga configuration setting gain pga_chn<2:0> gain (v/v) gain (db) v in range (v) 000 100.5 001 260.25 010 4120.125 011 8 18 0.0625 100 16 24 0.03125 101 32 30 0.015625 second- order integrator loop filter quantizer dac differential voltage input output bitstream 5-level flash adc MCP3903 sigma-delta modulator
MCP3903 ds25048b-page 24 ? 2011 microchip technology inc. 5.3.2 modulator input range and saturation point for a specified voltage reference value of 2.4v, the modulator specified differential input range is 500 mv. the input range is proportional to v ref and scales according to the v ref voltage. this range ensures the stability of the modulator over amplitude and frequency. outside of this range, the modulator is still functional, however its stability is no longer guaranteed and therefore it is not recommended to exceed this limit. the saturation point for the modulator is v ref /3 since the transfer function of the adc includes a gain of 3 by default (independent from the pga setting. see section 5.5 ?adc output coding? ). 5.3.3 boost mode the delta-sigma modulators also include an independent boost mode for each channel. if the corresponding boost<1:0> bit is enabled, the power consumption of the modulator is multiplied by 2 and its bandwidth is increased to be able to sustain amclk clock frequencies up to 8.192 mhz while keeping the adc accuracy. when disabled, the power consumption returns back to normal and the amclk clock frequencies can only reach up to 5 mhz without affecting adc accuracy.
? 2011 microchip technology inc. ds25048b-page 25 MCP3903 5.4 sinc 3 filter all adcs present in the MCP3903 include a decimation filter that is a third-order sinc (or notch) filter. this filter processes the multi-bit bitstream into 16 or 24 bits words (depending on the width configuration bit). the settling time of the filter is 3 dmclk periods. it is recommended to discard unsettled data to avoid data corruption which can be done easily by setting the dr_lty bit high in the status/com register. the resolution achievable at the output of the sinc filter (the output of the adc) is dependant on the osr and is summarized in the following table: for 24 -bit output mode (width = 1), the output of the sinc filter is padded with least significant zeros for any resolution less than 24 bits. for 16-bit output modes, the output of the sinc filter is rounded to the closest 16-bit number in order to conserve only 16-bit words and to minimize truncation error. the gain of the transfer function of this filter is 1 at each multiple of dmclk (typically 1 mhz) so a proper anti-aliasing filter must be placed at the inputs to attenuate the frequency content around dmclk, and keep the desired accuracy over the baseband of the converter. this anti-aliasing filter can be a simple first-order rc network, with a sufficiently low time constant to generate high rejection at dmclk frequency. equation 5-1: sinc filter transfer function h(z) where: the normal-mode rejection ratio (nmrr), or gain of the transfer function, is shown in the following equation: equation 5-2: magnitude of frequency response h(f) or: where: figure 5-2 shows the sinc filter frequency response: figure 5-2: sinc filter response with mclk = 4 mhz, osr = 64, prescale = 1. table 5-2: adc resolution vs. osr osr<1:0> osr adc resolution (bits) no missing codes 00 32 17 01 64 20 10 128 23 11 256 24 hz () 1z osr ? ? osr 1 z 1 ? ? () -------------------------------- - ?? ?? ?? 3 = z 2 fj dmclk --------------------- - ?? ?? exp = nmrr f () c f drclk -------------------- ? ?? ?? sin c f dmclk --------------------- - ? ?? ?? sin ---------------------------------------------- 3 = nmrr f () c f f d ---- - ? ?? ?? sin c f f s --- - ? ?? ?? sin ----------------------------- 3 = cx () sin x () sin x -------------- - = -120 -100 -80 -60 -40 -20 0 20 1 10 100 1000 10000 100000 1000000 input frequency (hz) magnitude (db)
MCP3903 ds25048b-page 26 ? 2011 microchip technology inc. 5.5 adc output coding the second order modulator, sinc 3 filter, pga, v ref and analog input structure all work together to produce the device transfer function for the analog to digital con- version, shown in equation 5-3 . the channel data is either a 16-bit or 24-bit word, presented in 23-bit or 15-bit plus sign, two?s complement format and is msb (left) justified. the adc data is two or three bytes wide depending on the width bit of the associated channel. the 16-bit mode includes a round to the closest 16-bit word (instead of truncation) in order to improve the accuracy of the adc data. in case of positive saturation (chn+ - chn- > v ref /3), the output is locked to 7fffff for 24 bit mode (7fff for 16 bit mode). in case of negative saturation (chn+ - chn- <-v ref /3), the output code is locked to 800000 for 24-bit mode (8000 for 16 bit mode). equation 5-3 is only true for dc inputs. for ac inputs, this transfer function needs to be multiplied by the transfer function of the sinc 3 filter (see equation 5-1 and equation 5-2 ). equation 5-3: 5.5.1 adc resolution as a function of osr the adc resolution is a function of the osr ( section 5.4 ?sinc3 filter? ). the resolution is the same for both channels. no matter what the resolution is, the adc output data is always presented in 24-bit words, with added zeros at the end if the osr is not large enough to produce 24-bit resolution (left justification). data_chn ch n+ ch n- ? () v ref+ v ref- ? ------------------------------------- ?? ?? 8,388,608 g 3 = data_chn ch n+ ch n- ? () v ref+ v ref- ? ------------------------------------- ?? ?? 32 768 ,g3 = (for 24-bit mode or width_chn = 1) (for 16-bit mode or width_chn = 0) table 5-3: osr = 256 output code examples adc output code (msb first) hexadecimal decimal 0111 1111 1111 1111 1111 1111 0x7fffff + 8,388,607 0111 1111 1111 1111 1111 1110 0x7ffffe + 8,388,606 0000 0000 0000 0000 0000 0000 0x000000 0 1111 1111 1111 1111 1111 1111 0xffffff -1 1000 0000 0000 0000 0000 0001 0x800001 - 8,388,607 1000 0000 0000 0000 0000 0000 0x800000 - 8,388,608 table 5-4: osr = 128 output code examples adc output code (msb first) hexadecimal decimal 23-bit resolution 0111 1111 1111 1111 1111 111 0 0x7ffffe + 4,194,303 0111 1111 1111 1110 1111 110 0 0x7ffffc + 4,194,302 0000 0000 0000 0000 0000 000 0 0x000000 0 1111 1111 1111 1111 1111 111 0 0xfffffe -1 1000 0000 0000 0000 0000 001 0 0x800002 - 4,194,303 1000 0000 0000 0000 0000 000 0 0x800000 - 4,194,304
? 2011 microchip technology inc. ds25048b-page 27 MCP3903 5.6 voltage reference 5.6.1 internal voltage reference the MCP3903 contains an internal voltage reference source specially designed to minimize drift over temperature. in order to enable the internal voltage reference, the vrefext bit in the configuration register must be set to 0 (default mode). this internal v ref supplies reference voltage to both channels. the typical value of this voltage reference is 2.35v 2%. the internal reference has a very low typical temperature coefficient of 5 ppm/c, allowing the out- put codes to have minimal variation with respect to temperature since they are proportional to (1/v ref ). the noise of the internal voltage reference is low enough not to significantly degrade the snr of the adc if compared to a precision external low-noise voltage reference. the output pin for the internal voltage reference is refin+/out. when the internal voltage reference is enabled, refin- pin should always be connected to agnd. for optimal adc accuracy, appropriate bypass capacitors should be placed between refin+/out and agnd. de-coupling at the sampling frequency, around 1 mhz, is important for any noise around this frequency will be aliased back into the conversion data. 0.1 f ceramic and 10 f tantalum capacitors are recommended. these bypass capacitors are not mandatory for correct adc operation, but removing these capacitors may degrade accuracy of the adc. the bypass capacitors also help for applications where the voltage reference output is connected to other circuits. in this case, additional buffering may be needed as the output drive capability of this output is low. 5.6.2 differential external voltage inputs when the vrefext bit is high, the two reference pins (refin+/out, refin-) become a differential voltage reference input. the voltage at the refin+/out is noted v ref + and the voltage at the refin- pin is noted v ref -. the differential voltage input value is shown in the following equation: equation 5-4: the specified v ref range is from 2.2v to 2.6v. the refin- pin voltage (v ref -) should be limited to 0.3v. typically, for single-ended reference applications, the refin- pin should be directly connected to agnd. table 5-5: osr = 64 output code examples adc output code (msb first) hexadecimal decimal 20-bit resolution 0111 1111 1111 1111 1111 0 0 0 0 0x7ffff0 + 524, 287 0111 1111 1111 1111 1110 0 0 0 0 0x7fffe0 + 524, 286 0000 0000 0000 0000 0000 0 0 0 0 0x000000 0 1111 1111 1111 1111 1111 0 0 0 0 0xfffff0 -1 1000 0000 0000 0000 0001 0 0 0 0 0x800010 - 524,287 1000 0000 0000 0000 0000 0 0 0 0 0x800000 - 524, 288 table 5-6: osr = 32 output code examples adc output code (msb first) hexadecimal decimal 17-bit resolution 0111 1111 1111 1111 1 0 0 0 0 0 0 0 0x7fff80 + 65, 535 0111 1111 1111 1111 0 0 0 0 0 0 0 0 0x7fff00 + 65, 534 0000 0000 0000 0000 0 0 0 0 0 0 0 0 0x000000 0 1111 1111 1111 1111 1 0 0 0 0 0 0 0 0xffff80 -1 1000 0000 0000 0000 1 0 0 0 0 0 0 0 0x800080 - 65,535 1000 0000 0000 0000 0 0 0 0 0 0 0 0 0x800000 - 65, 536 v ref =v ref + - v ref -
MCP3903 ds25048b-page 28 ? 2011 microchip technology inc. 5.7 power-on reset the MCP3903 contains an internal por circuit that monitors analog supply voltage av dd during operation. the typical threshold for a power-up event detection is 4.2v 5%. the por circuit has a built-in hysteresis for improved transient spikes immunity that has a typical value of 200 mv. proper decoupling capacitors (0.1 f ceramic and 10 f tantalum) should be mounted as close as possible to the av dd pin, providing additional transient immunity. figure 5-3 illustrates the different conditions at power-up and a power-down event, in typical conditions. all internal dc biases are not settled until at least 50 s after system por. any data ready pulses during this time after system reset should be ignored. after por, data ready pulses are present at the pin with all the default conditions in the configuration regis- ters. both av dd and dv dd power supplies are independent. since av dd is the only power supply that is monitored, it is highly recommended to power up dv dd first as a power-up sequence. if av dd is powered up first, it is highly recommended to keep the reset pin low during the whole power-up sequence. figure 5-3: power-on reset operation. 5.8 reset effect on delta sigma modulator/sinc filter when the reset pin is low, both adcs will be in reset and output code 0x0000h. the reset pin performs a hard reset (dc biases still on, part ready to convert) and clears all charges contained in the sigma delta modulators. the comparator outputs are 0011 for each adc. the sinc filters are all reset, as well as their double output buffers. this pin is independent of the serial interface. it brings the config registers to the default state. when reset is low, any write with the spi interface will be disabled and will have no effect. all output pins (sdo, dr , mdat0/1) are high impedance, and no clock is propagated through the chip. 5.9 phase delay block the MCP3903 incorporates a phase delay generator which ensures that the six adcs are converting the inputs with a fixed delay between them. the six adcs are synchronously sampling but the averaging of modulator outputs is delayed so that the sinc filter outputs (thus the adc outputs) show a fixed phase delay, as determined by the phase register setting. the phase register is composed of three bytes: phasec<7:0>, phaseb<7:0>, phasea<7:0>. each byte is a 7 bit + sign msb first, two's complement code that represents the amount of delay between each pair of adcs. the phasec byte represents the delay between channel 4 and channel 5 (pair c). the phaseb byte represents the delay between channel 2 and channel 3 (pair b). the phasea byte represents the delay between channel 0 and channel 1 (pair a). the reference channel is the odd channel (channel 1/ 3/5). when phasen<7:0> is positive, channel 0/2/4 is lagging versus channel 1/3/5 otherwise it is leading. the amount of delay between two adc conversions is given by the following formula: equation 5-5: the timing resolution of the phase delay is 1/dmclk or 1 s in the default configuration with mclk = 4 mhz. the data ready signals are affected by the phase delay settings. typically, the time difference between the data ready pulses of channel 0 and channel 1 is equal to the phase delay setting. av dd 5v 4.2v 4v 0v device mode reset proper operation reset time 50 s t por note: a detailed explanation of the data ready pins (drn ) with phase delay is present in section 6.10 ?data ready pulses (drn)? . delay phase register code dmclk ------------------------------------------------- - =
? 2011 microchip technology inc. ds25048b-page 29 MCP3903 5.9.1 phase delay limits the phase delay can only go from -osr/2 to +osr/2 - 1. this sets the fine phase resolution. the phase register is coded with 2's complement. if larger delays between the two channels from the same pair are needed, they can be implemented exter- nally to the chip with an mcu. a fifo in the mcu can save incoming data from the leading channel for a number n of drclk clocks. in this case, drclk would represent the coarse timing resolution, and dmclk the fine timing resolution. the total delay will then be equal to: delay = n/drclk + phase/dmclk the phase delay register can be programmed once with the osr=256 setting and will adjust to the osr automatically afterward without the need to change the value of the phase register. ? osr=256 : the delay can go from -128 to +127. phasen<7> is the sign bit. phasen<6> is the msb and phasen<0> the lsb. ? osr=128: the delay can go from -64 to +63. phasen<6> is the sign bit. phasen<5> is the msb and phasen<0> the lsb. ? osr=64 : the delay can go from -32 to +31. phasen<5> is the sign bit. phasen<4> is the msb and phasen<0> the lsb. ? osr=32: the delay can go from -16 to +15. phasen<4> is the sign bit. phasen<3> is the msb and phasen<0> the lsb. 5.10 crystal oscillator the MCP3903 includes a pierce-type crystal oscillator with very high stability and ensures very low tempco and jitter for the clock generation. this oscillator can handle up to 16.384 mhz crystal frequencies, provided that proper load capacitances and quartz quality factor are used. for keeping specified adc accuracy, amclk should be kept between 1 and 5 mhz with boost off or 1 and 8.192 mhz with boost on. larger mclk frequencies can be used, provided the prescaler clock settings allow the amclk to respect these ranges. for a proper start-up, the load capacitors of the crystal should be connected between osc1 and dgnd and between osc2 and dgnd. they should also respect the following equation: equation 5-6: when clkext=1, the crystal oscillator is bypassed by a digital buffer to allow direct clock input for an external clock. table 5-7: phase values with mclk = 4 mhz, osr = 256 phase register value hex delay (ch0/2/4 relative to ch1/3/5) 01111111 0x7f + 127 s 01111110 0x7e + 126 s 00000001 0x01 + 1 s 00000000 0x00 0 s 11111111 0xff - 1 s 10000001 0x81 - 127 s 10000000 0x80 -128 s r m 1.6 10 6 1 f c load ---------------------------- - ?? ?? 2 < where: f = crystal frequency in mhz c load = load capacitance in pf including parasitics from the pcb r m = motional resistance in ohms of the quartz
MCP3903 ds25048b-page 30 ? 2011 microchip technology inc. 6.0 serial interface description 6.1 overview the MCP3903 device is compatible with spi modes 0,0 and 1,1. data is clocked out of the MCP3903 on the falling edge of sck, and data is clocked into the MCP3903 on the rising edge of sck. in these modes, sck can idle either high or low. each spi communication starts with a cs falling edge and stops with the cs rising edge. each spi communication is independent. when cs is high, sdo is in high impedance, and transitions on sck and sdi have no effect. additional controls: reset , dr are also provided on separate pins for advanced communication. the MCP3903 interface has a simple command structure. the first byte transmitted is always the control byte that is 8 bits wide and is followed by data bytes that are 24 bits wide. both adcs are continuously converting data by default and can be reset or shutdown through a config register setting. since each adc data is either 16 or 24 bits (depending on the width bits), the internal registers can be grouped together with various configurations (through the read bits) in order to allow easy data retrieval within only one communication. for device reads, the internal address counter can be automatically incre- mented in order to loop through groups of data within the register map. the sdo will then output the data located at the address (a<4:0>) defined in the con- trol byte and then address+1 depending on the read<1:0> bits which select the groups of registers. these groups are defined in section 7.1 ?adc chan- nel data output registers? (register map). the data ready pins (drn) can be used as an interrupt for an mcu and outputs pulses when new adc channel data is available. the reset pin acts like a hard reset and can reset the part to its default power-up configuration. 6.2 control byte the control byte of the MCP3903 contains two device address bits a<6:5>, 5 register address bits a<4:0>, and a read/write bit (r/w). the first byte transmitted to the MCP3903 is always the control byte. figure 6-1: control byte. the default device address bits are 01 . a read on undefined addresses will give an all zeros output on the first and all subsequent transmitted bytes. a write on an undefined address will have no effect and will not incre- ment the address counter either. the register map is defined in section 7.1 ?adc channel data output registers? . 6.3 reading from the device the first data byte read is the one defined by the address given in the control byte. after this first byte is transmitted, if cs pin is maintained low, the communication continues and the address of the next transmitted byte is determined by the status of the read bits in the status/com register. multiple looping configurations can be defined through the read<1:0> bits for the address increment (see 6.6 ?spi mode 1,1 - clock idle high, read/write examples? ? ). 6.4 writing to the device the first data byte written is the one defined by the address given in the control byte. the write communication automatically increments the address for subsequent bytes. the address of the next transmitted byte within the same communication (cs stays low) is the next address defined on the register map. at the end of the register map, the address loops to the beginning of the register map. writing a non-writable register has no effect. sdo pin stays high impedance during a write communication. 6.5 spi mode 0,0 - clock idle low, read/write examples in this spi mode, the clock idles low. for the MCP3903, this means that there will be a rising edge before there is a falling edge. a6 a5 a4 a3 a2 a1 a0 r/w read write bit register (0) (1) address bits device address bits
? 2011 microchip technology inc. ds25048b-page 31 MCP3903 figure 6-2: device read (spi mode 0,0 - clock idles low) . figure 6-3: device write (spi mode 0,0 - clock idles low). 6.6 spi mode 1,1 - clock idle high, read/write examples in this spi mode, the clock idles high. for the MCP3903, this means that there will be a falling edge before there is a rising edge. figure 6-4: device read (spi mode 1,1 - clock idles high). sck sdi sdo cs r/w a6 a5 a4 a3 a2 a1 a0 d23 22 21 20 19 18 17 16 (address) 24 bit data d15 06 05 04 03 02 01 data transitions on the falling edge mcu and mcp3901 latch bits on the rising edge 00 d23 (of address + 1 data) hi-z hi-z hi-z d07 1 32 note: sck sdi sdo cs r/w a6 a5 a4 a3 a2 a1 a0 d23 22 21 20 19 18 17 d15 (address) data d6 d5 d4 d3 d2 d1 d23 of (address + 1) data 16 data transitions on the falling edge mcu and mcp3901 latch bits on the rising edge d0 hi-z hi-z hi-z d7 1 32 sck sdi sdo cs a6 a5 a4 a3 a2 a1 a0 22 21 20 19 18 17 d8 (address) data d6 d5 d4 d3 d2 d1 data transitions on the falling edge mcu and mcp3901 latch bits on the rising edge d0 hi-z hi-z 23 d7 r/w hi-z d16 1 32
MCP3903 ds25048b-page 32 ? 2011 microchip technology inc. figure 6-5: device write (spi mode 1,1 - clock idles high). 6.7 read continuously channel data, looping on address sets if the user wishes to read back any of the adc channels continuously, or all channels continuously, the internal address counter of the MCP3903 can be set to loop on specific register sets. in this case, there is only one control byte on sdi to start the communication. the part stays within the same loop until cs returns high. this internal address counter allows the following functionality: ? read one adc channel data continuously ? read all adc channel data continuously (all adc data can be independent or linked with drn_mode settings) ? read continuously the entire register map ? read continuously each separate register ? read continuously all configuration registers ? write all configuration registers in one communication (see figure 6-6 ) the status/com register contains the loop settings for the internal address counter (read<1:0>). the internal address counter can either stay constant (read<1:0>=00) and continuously read the same byte, or it can auto-increment and loop through the register groups defined below (read<1:0>=01), register types (read<1:0>=10) or the entire register map (read<1:0>=11). each channel is configured independently as either a 16-bit or 24-bit data word, depending on the setting of the corresponding width bit in the config register. for continuous reading, in the case of width=0 (16-bit), the lower byte of the adc data is not accessed and the part jumps automatically to the following address (the user does not have to clock out the lower byte since it becomes undefined for width=0). the following figure represents a typical continuous read communication with the default settings (drmode<1:0>=00, read<1:0>=10) for both width settings. this configuration is typically used for power metering applications. figure 6-6: typical continuous read communication. sck sdi sdo cs r/w a6 a5 a4 a3 a2 a1 a0 23 22 21 20 19 18 17 (address) data d6 d5 d4 d3 d2 d1 d16 data transitions on the falling edge mcu and mcp3901 latch bits on the rising edge d0 hi-z hi-z d7 hi-z d08 1 32 5 ch5 ch5 5 ch5 ch5
? 2011 microchip technology inc. ds25048b-page 33 MCP3903 6.7.1 continuous read all adcs are powered up with their default configurations, and begin to output data ready pulses immediately (reset<5:0> and shutdown<5:0> bits are off by default). the default output codes for both adcs are all zeros.the default modulator output for both adcs is 0011 (corresponding to a theoretical zero voltage at the inputs). the default phase is zero between the two channels. it is recommended to enter into adc reset mode for both adcs just after power-up because the desired MCP3903 register configuration may not be the default one and in this case, the adc would output undesired data. within the adc reset mode (reset<5:0>=11 1111), the user can configure the whole part with a single communication. the write commands automatically increment the address so the user can start writing the phase register and finish with the config register in only one communication (see figure 6-6). the reset<5:0> bits are in the config register to allow it to exit soft reset mode and have the whole part configured and ready to run in only one command. the following internal registers are defined as types: 6.8 situations that reset adc data immediately after the following actions, the adcs are reset and automatically restarted in order to provide proper operations: 1: change in phase register 2: change in the osr setting 3: change in the prescaler setting 4: overwrite of identical phase register value 5: change in extclk bit in the config register modifying internal oscillator state. after these temporary resets, the adcs go back to normal operation with no need for an additional command. these are also the settings where the dr position is affected. the phase register can be used to soft reset the adc without using the reset bits in the configuration register. 6.9 line cycle sampling options since the amclk range can go up to 5 mhz, the MCP3903 is able to accommodate 256 output samples per line cycles with line frequencies up to 76.2hz at osr=64. . figure 6-7 illustrates operating the part in this manner (timings not to scale, functional description only). all channels are continuously converting during normal operation of the device except when it is in sleep mode by using the reset bit, or if reset is low. the following figure represents the clocking scheme and how the config prescale<1:0> bits and osr<1:0> bits registers is used to modify the clock prescale and oversampling ratio. for example, if a data ready pulse occurs while adc data (a) is being transmitted on spi, this data will not be corrupt in any way. after cs is toggled low to begin another transmission, the next data (b) would be present in the output buffer ready for transmission. table 6-1: register groups group addresses pair a, channel 0/1 0x00 - 0x01 pair b, channel 2/3 0x02 - 0x03 pair c, channel 4/5 0x04 - 0x05 mod, phase, gain 0x06 - 0x08 status, config 0x09 - 0x0a table 6-2: register types type addresses adc data 0x00 - 0x05 control 0x06 - 0x0a table 6-1: mclk frequencies for line sampling output samples / line cycle f line = 45 hz osr = 64 f line = 65 hz osr = 64 f d mclk f d mclk 64 2.8 ksps 737.28 khz 4.2 ksps 1.075 mhz 128 5.76 ksps 1.475 mhz 8.4 ksps 2.15 mhz 256 11.5 ksps 2.949 mhz 16.7 ksps 4.3 mhz
MCP3903 ds25048b-page 34 ? 2011 microchip technology inc. figure 6-7: standard device operation. 6.10 data ready pulses (dr n ) to ensure that all channel adc data are present at the same time for spi read, regardless of phase delay set- tings for either or both channels, there are two sets of latches in series with both the data ready and the ?read start? triggers. the first set of latches holds each output when data is ready and latches both outputs together when drmode<1:0>=00. when this mode is on, both adcs work together and produce one set of available data after each data ready pulse (that corresponds to the lagging adc data ready). the second set of latches ensures that when reading starts on an adc output, the corresponding data is latched so that no data corruption can occur. if an adc read has started, in order to read the following adc output, the current reading needs to be completed (all bits must be read from the adc output data registers). 6.10.1 data ready pins (dr n) control using drn_mode bits there are four modes that control the data ready pulses, and these modes are set with the drn_mode<1:0> bits in the status/com register. for power metering applications, drn_mode<1:0>=00 is recommended (default mode). the position of data ready pulses vary with respect to this mode, to the osr and to the phase settings: ? drn_mode<1:0> = 11: both data ready pulses from adc channel 0/2/4 and adc channel 1/3/5 are output on dr pin. ? drn_mode<1:0> = 10: data ready pulses from adc channel 1/3/5 are output on the correspond- ing drn pin. data ready pulses from adc chan- nel 0/2/4 are not present on the pin. ? drn_mode<1:0> = 01: data ready pulses from adc channel 0/2/4 are output on the correspond- ing drn pin. data ready pulses from adc chan- nel 1/3/5 are not present on the pin. ? drn_mode<1:0> = 00: (recommended, and default mode). data ready pulses from the lagging adc between the two are output on dr pin. the lagging adc depends on the phase register and on the osr. in this mode the two adcs are linked together so their data is latched together when the lagging adc output is ready. 6.10.2 dr pulses with shutdown or reset conditions there will be no data ready pulses if drn_mode<1:0>=00 when either one or both of the adcs of the corresponding pair are in reset or shut- down. in mode 00, a data ready pulse only happens when both adcs of the corresponding pair are ready. any data ready pulse will correspond to one data on both adcs. the two adcs are linked together and act as if there was only one channel with the combined data of both adcs. this mode is very practical when both adc channel data retrieval and processing need to be synchronized, as in power metering applications. figure 6-8 represents the behavior of the data ready pin with the different drn_mode and dr_lty configurations, while shutdown or resets are applied. 1 / f data 1 / f line dr n 1 / f data osc1/mclki cs sck sdi spi sdo note: if drn_mode<1:0>=11, the user will still be able to retrieve the data ready pulse for the adc not in shutdown or reset, i.e. only 1 adc channel needs to be awake.
? 2011 microchip technology inc. ds25048b-page 35 MCP3903 figure 6-8: data ready behavior. d0 d1 d2 d0 d1 d2 d3 d4 d5 d3 d4 d5 d0 d1 d2 d3 d4 d5 d6 d7 d8 d1 d3 d5 d6 d7 d8 d10 d12 d0 d2 d4 d9 d11 d13 d14 d6 d6 d12 d9 d13 d16 d17 d18 d19 d21 d24 d15 d20 d22 d25 d26 d7 d8 d9 d10 d11 d10 d11 d12 d10 d7 d8 d9 d23 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 d12 d13 d14 d15 d16 d0 d1 d2 d4 d5 d3 d7 d8 d9 d10 d11 d12 d13 d6 d15 d16 d14 d0 d1 d2 d6 d10 d11 d12 d13 d11 d13 d14 d15 d16 d12 d13 d14 d14 d28 d29 d31 d33 d27 d30 d32 d34 d15 d16 d17 d8 d7 d9 d4 d5 d3 reset<1> or shutdown<1> reset<0> or shutdown<0> reset d0 d1 d2 d3 d4 d5 d0 d1 d2 d3 d4 d5 d6 d7 d8 d1 d3 d5 d6 d7 d8 d11 d13 d0 d2 d4 d10 d12 d14 d15 d6 d9 d13 d17 d18 d21 d24 d16 d19 d22 d25 d26 d10 d11 d12 d10 d8 d9 d23 d11 d12 d13 d14 d28 d29 d31 d33 d27 d30 d32 d34 d14 d15 d16 d0 d1 d2 d3 d4 d5 d12 d11 d13 d15 d16 d17 d8 d9 d10 d7 phase < 0 phase = 0 phase > 0 d6 d7 drclk period drclk period internal reset synchronisation (1 dmclk period) 3*drclk period 3*drclk period d14 d9 d20 drmode=00; dr drmode=01; dr drmode=10; dr drmode=11; dr drmode=00; dr drmode=01; dr drmode=10; dr drmode=11; dr drmode=00; dr drmode=01; dr drmode=10; dr drmode=11; dr drmode=00 : select the lagging data ready drmode=01 : select the data ready on channel 0 drmode=10 : select the data ready on channel 1 drmode=11 : select both data ready data ready pulse that appears only when dr_lty=0 drclk period 1 dmclk period
MCP3903 ds25048b-page 36 ? 2011 microchip technology inc. 6.11 data ready pulse with phase delay to ensure that both channel adc data from the same pair are present at the same time for spi read, regard- less of phase delay settings for either or both channels, there are two sets of latches in series with both the data ready and the reading start triggers. the first latch is set on whichever channel is the lagging channel (relative to the other channel, in a single channel pair). the second latch is set when an adc output read command is issued, ensuring synchronized data ready pulses. figure 6-9: internal latches synchronizing data ready pulses with phase delay present (single channel pair shown). 6.11.1 data ready link when drlink=0, the three pairs of adcs are independent from each other. the data readys and the latches for the output data only depend on both adcs in the pair. when another adc (not in the pair) is put in shutdown or reset, it has no effect. when drlink=1, all adcs are linked together. the drn_mode<1:0> are all set internally to 00. all drn_mode<1:0> bits are not taken into account. all six channel adc data are latched synchronously with the most lagging adc channel of the six. all three dra , drb and drc data ready pins are giving the same output that is synchronized with the most lagging adc of the six channels. only one pin can be connected to the mcu in this mode, which saves two connection ports on the mcu. in this mode, if any channel is in shutdown or reset mode, no data ready is present on any of the dra/ dr b/ dr c pins. the part acts as if there was only one adc channel with 6x24 bits. depending on the read modes, the adc data can be retrieved by pair (read by group) or all together (read by type). any time a new read command is per- formed, the adc outputs are re-latched. in order to avoid loss of data or bad synchronization, the read mode by types is recommended (read<1:0>=10) so that all data can be latched once at the beginning of the read. in the read mode by group (read<1:0>=01) mode, the data will be relatched every time the part accesses to each group or pair of adcs. chn adc latch spi serial interface chn adc latch synchronized data ready pulses
? 2011 microchip technology inc. ds25048b-page 37 MCP3903 7.0 internal registers the addresses associated with the internal registers are listed below. all registers are 24 bits long and can be addressed separately . a detailed description of the registers follows. . the following table shows how the internal address counter will loop on specific register groups and types. 7.1 channel output registers the adc channel data output registers always contain the most recent a/d conversion data for each channel. these registers are read-only. they can be accessed independently or linked together (with read<1:0> bits). these registers are latched when an adc read communication occurs. when a data ready event occurs during a read communication, the most current adc data is also latched to avoid data corruption issues. the three bytes of each channel are updated synchronously at a drclk rate. the three bytes can be accessed separately if needed, but are refreshed synchronously. the coding is 23-bit + sign two?s complement (see section 5.5). table 7-1: internal register summary address name bits r/w description 0x00 channel 0 24 r channel 0 adc data <23:0>, msb first, left justified 0x01 channel 1 24 r channel 1 adc data <23:0>, msb first, left justified 0x02 channel 2 24 r channel 2 adc data <23:0>, msb first, left justified 0x03 channel 3 24 r channel 3 adc data <23:0>, msb first, left justified 0x04 channel 4 24 r channel 4 adc data <23:0>, msb first, left justified 0x05 channel 5 24 r channel 5 adc data <23:0>, msb first, left justified 0x06 mod 24 r/w delta sigma modulators output value 0x07 phase 24 r/w phase delay configuration register 0x08 gain 24 r/w gain configuration register 0x09 status/com 24 r/w status/communication register 0x0a config 24 r/w configuration register table 7-2: continuous read options, looping on internal addresses function address read<1:0> = ?01? = ?10? =?11? channel 0 0x00 group type loop entire register map channel 1 0x01 channel 2 0x02 group channel 3 0x03 channel 4 0x04 group channel 5 0x05 mod 0x06 group type phase 0x07 gain 0x08 status/ com 0x09 group config 0x0a table 7-3: adc output registers name bits address cof channel 0 24 0x00 r channel 1 24 0x01 r channel 2 24 0x02 r channel 3 24 0x03 r channel 4 24 0x04 r channel 5 24 0x05 r
MCP3903 ds25048b-page 38 ? 2011 microchip technology inc. register 7-1: channel register r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 d23 (msb) d22 d21 d20 d19 d18 d17 d16 bit 23 bit 16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 d15 d14 d13 d12 d11 d10 d9 d8 bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 d7 d6 d5 d4 d3 d2 d1 d0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23:0 24-bit adc output data of the corresponding channel
? 2011 microchip technology inc. ds25048b-page 39 MCP3903 7.2 mod register the mod register contains the most recent modulator data output. the default value corresponds to an equivalent input of 0v on each adc. each bit in this register corresponds to one comparator output on one of the channels. this register should be used as a read-only register. (note 1) . this register is updated at the refresh rate of dmclk (typically 1 mhz with mclk = 4 mhz). the default state for this register is 001100110011001100110011. table 7-4: modulator output register name bits address cof mod 24 0x06 r/w register 7-2: mod register r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-1 r/w-1 comp3_ch5 comp2_ch5 comp1_ch5 comp0_ch5 comp3_ch4 comp2_ch4 comp1_ch4 comp0_ch4 bit 23 bit 16 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-1 r/w-1 comp3_ch3 comp2_ch3 comp1_ch3 comp0_ch3 comp3_ch2 comp2_ch2 comp1_ch2 comp0_ch2 bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-1 r/w-1 comp3_ch1 comp2_ch1 comp1_ch1 comp0_ch1 comp3_ch1 comp2_ch0 comp1_ch0 comp0_ch0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23:20 compn_ch5: comparator outputs from adc channel 5 bit 19:16 compn_ch4: comparator outputs from adc channel 4 bit 15:12 compn_ch3: comparator outputs from adc channel 3 bit 11:8 compn_ch2: comparator outputs from adc channel 2 bit 7:4 compn_ch1: comparator outputs from adc channel 1 bit 3:0 compn_ch0: comparator outputs from adc channel 0
MCP3903 ds25048b-page 40 ? 2011 microchip technology inc. 7.3 phase register the phase register is composed of three bytes: phasec<7:0>, phaseb<7:0>, phasea<7:0>. each byte is a 7 bit + sign msb first, two's complement code that represents the amount of delay between each pair of adcs. the phasec byte represents the delay between channel 4 and channel 5 (pair c). the phaseb byte represents the delay between channel 2 and channel 3 (pair b). the phasea byte represents the delay between channel 0 and channel 1 (pair a). the reference channel is the odd channel (channel 1/ 3/5). when phasen<7:0> is positive, channel 0/2/4 is lagging versus channel 1/3/5 otherwise it is leading. the delay is calculated by the following formula: delay = phase register code / dmclk. table 7-5: phase register name bits address cof phase 24 0x07 r/w register 7-3: phase register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phasec7 phasec6 phasec5 phasec4 phasec3 phasec2 phasec1 phasec0 bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phaseb7 phaseb6 phaseb5 phaseb4 phaseb3 phaseb2 phaseb1 phaseb0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 phasea7 phasea6 phasea5 phasea4 phasea3 phasea2 phasea1 phasea0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23:16 phasecn: ch4 relative to ch5 phase delay bit 15:8 phasebn: ch2 relative to ch3 phase delay bit 7:0 phasean: ch0 relative to ch1 phase delay
? 2011 microchip technology inc. ds25048b-page 41 MCP3903 7.4 gain configuration register this register contains the gain register table 7-6: gain register name bits address cof gain 24 0x08 r/w register 7-4: gain register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pga2_ch5 pga1_ch5 pga0_ch5 boost_ ch5 boost_ ch4 pga2_ch4 pga1_ch4 pga0_ch4 bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pga2_ch3 pga1_ch3 pga0_ch3 boost_ ch3 boost_ ch2 pga2_ch2 pga1_ch2 pga0_ch2 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pga2_ch1 pga1_ch1 pga0_ch1 boost_ ch1 boost_ ch0 pga2_ch0 pga1_ch0 pga0_ch0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit pga_chn: pga setting for channel n 111 = reserved (gain = 1) 110 = reserved (gain = 1) 101 = gain is 32 100 = gain is 16 011 = gain is 8 010 = gain is 4 001 = gain is 2 000 = gain is 1 bit boost_chn current scaling for high speed operation for channel n 1 = channel has current x 2 0 = channel has normal current
MCP3903 ds25048b-page 42 ? 2011 microchip technology inc. 7.5 status/com register - status and communication register 7.5.1 data ready latency - dr_lty this bit determines if the data ready pulses correspond to settled data or unsettled data from each sinc 3 filter. unsettled data will provide data ready pulses every drclk period. settled data will wait for 3 drclk periods before giving data ready pulses and will then give data ready pulses every drclk period. 7.5.2 data ready high z mode - dr_hiz using this bit, the user can connect multiple chips with the same data ready pin with a pull up resistor (dr_hiz =0) or a single chip with no external compo- nent (dr_hiz =1) 7.5.3 data ready mode - drn_mode these bits control which adc data ready is present on the data ready pin. when the bits are set to 00, the output of the two adcs are latched synchronously at the moment of the data ready event. this prevents bad synchronization between the two adcs. the output is also latched at the beginning of a reading, in order not to be updated during a read, and not to give erroneous data. if one of the channels is in reset or shutdown, only one of the data ready pulses is present and the situation is similar to drn_mode<1:0> = 01 or 10. in the 01,10 and 11 modes, the data is latched at the beginning of a reading, in order to prevent the case of erroneous data when a data ready pulse happens when reading. 7.5.4 data ready status flag - drstatus_chn these bits indicate the data ready status of each chan- nel. these flags are set to logic high after being the status/com register has been read. these bits are cleared when a data ready event has happened on its respective adc. writing these bits has no effect. table 7-7: status/com register name bits address cof status/com 24 0x09 r/w note: these bits are useful if multiple devices share the same drn output pin (dr_hiz =0) in order to understand which device the data ready event occured from. in case the drn_mode=00 (linked adcs), these data ready status bits will be updated synchronously upon the same event (lagging adc is ready). these bits are also useful in systems where the drn pins are not used to save mcu i/o. register 7-5: status/com register r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 read1 read0 wmode width_ch5 width_ch4 width_ch3 width_ch2 width_ch1 bit 23 bit 16 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 width_ch0 dr_lty dr_hiz dr_link drc_mode1 drc_mode0 drb_mode1 drb_mode0 bit 15 bit 8 r/w-0 r/w-0 r-1 r-1 r-1 r-1 r-1 r-1 dra_mode1 dra_mode0 drstatus_ch5 drstatus_ch4 drstatus_ch3 drstatus_ch2 drstatus_ch1 drstatus_ch0 bit 7 bit 0 bit 23:22 read[1:0]: address loop setting 11 = address counter incremented, cycle through entire register map 10 = address counter loops on register types (default) 01 = address counter loops on register groups 00 = address not incremented, continually read single register bit 21 wmode: write mode bit (internal use only) 1 = static addressing write mode 0 = incremental addressing write mode ( default)
? 2011 microchip technology inc. ds25048b-page 43 MCP3903 bit 20:15 width_chn adc channels output data word width control 1 = 24-bit mode for the corresponding channel 0 = 16-bit mode for the corresponding channel (default) bit 14 dr_lty: data ready latency control for dra , drb , and drc pins 1 = true ?no latency? conversion, data ready pulses after 3 drclk periods (default) 0 = unsettled data is available after every drclk period bit 13 dr_hiz : data ready pin inactive state control for dra , drb , and drc pins 1 = the default state is a logic high when data is not ready 0 = the default state is high impedance when data is not ready (default) bit 12 dr_link data ready link control 1 = data ready link turned on, all channels linked and data ready pulses from the most lagging adc are present on each drn pin 0 = data ready link tunred off (default) bit 11:10 drc_mode[1:0] 11 = both data ready pulses from ch4 and ch5 are output on drc pin. 10 = data ready pulses from ch5 are output on drc pin. data ready pulses r from ch4 are not pres- ent on the pin. 01 = data ready pulses from ch4 are output on drc pin. data ready pulses from ch5 are not present on the pin. 00 = data ready pulses from the lagging adc channel between the two are output on drc pin. the lagging adc channel depends on the phase register and on the osr. (default) bit 9:8 drb_mode[1:0] 11 = both data ready pulses from ch2 and ch3 are output on drb pin. 10 = data ready pulses from ch3 are output on drb pin. data ready pulses from ch2 are not present on the pin. 01 = data ready pulses from ch2 are output on drb pin. data ready pulses from ch3 are not present on the pin. 00 = data ready pulses from the lagging adc channel between the two are output on drb pin. the lagging adc channel depends on the phase register and on the osr. (default) bit 7:6 dra_mode[1:0] 11 = both data ready pulses from ch0 and ch1 are output on dra pin. 10 = data ready pulses from ch1 are output on dra pin. data ready pulses from ch0 are not present on the pin. 01 = data ready pulses from ch0 are output on dra pin. data ready pulses from ch1 are not present on the pin. 00 = data ready pulses from the lagging adc channel between the two are output on dra pin. the lagging adc channel depends on the phase register and on the osr. (default) bit 5:0 drstatus_chn: data ready status 1 = data not ready (default) 0 = data ready register 7-5: status/com register (continued)
MCP3903 ds25048b-page 44 ? 2011 microchip technology inc. 7.6 config register - configuration register table 7-8: config register name bits address cof config 24 0x0a r/w register 7-6: co nfig register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 reset_ch5 reset_ch4 reset_ch3 reset_ch2 reset_ch1 reset_ch0 shutdown_ch5 shutdown_ch4 bit 23 bit 16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 shutdown_ ch3 shutdown_ ch2 shutdown_ch1 shutdown_ch0 dither_ch5 dither_ch4 dither_ch3 dither_ch2 bit 15 bit 8 r/w-1 r/w-1 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 dither_ch1 dither_ch0 osr1 osr0 prescale1 prescale0 extvref extclk bit 7 bit 0 bit 23:18 reset_chn: reset mode setting for adcs 1 = reset mode for the corresponding adc channel on 0 = reset mode for the corresponding adc chnnel off (default) bit 17:12 shutdown_chn: shutdown mode setting for adcs 1 = shutdown mode for the corresponding adc channel on 0 = shutdown mode for the corresponding adc channel off (default) bit 11:6 dither_chn: control for dithering circuit for idle tones cancellation 1 = dithering circuit for the corresponding adc channel on (default) 0 = dithering circuit for the corresponding adc channel off bit 5:4 osr[1:0] oversampling ratio for delta sigma a/d conversion (all channels, f d / f s ) 11 = 256 10 = 128 01 = 64 (default) 00 = 32 bit 3:2 prescale[1:0] internal master clock (amclk) prescaler value 11 = amclk = mclk/ 8 10 = amclk = mclk/ 4 01 = amclk = mclk/ 2 00 = amclk = mclk (default) bit 1 extvref internal voltage reference shutdown control 1 = internal voltage reference disabled 0 = internal voltage reference enabled (default) bit 0 extclk clock mode 1 = clock mode (internal oscillator disabled - lower power) 0 = xt mode - a crystal must be placed between osc1/osc2 (default)
? 2011 microchip technology inc. ds25048b-page 45 MCP3903 8.0 packaging information 8.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead ssop (5.30 mm) example MCP3903 3 e e/ss 1124256 28-lead ssop (5.30 mm) example MCP3903 3 e i/ss 1124256
MCP3903 ds25048b-page 46 ? 2011 microchip technology inc.
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? 2011 microchip technology inc. ds25048b-page 47 MCP3903 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
MCP3903 ds25048b-page 48 ? 2011 microchip technology inc.
? 2011 microchip technology inc. ds25048b-page 51 MCP3903 appendix a: revision history revision b (july 2011) ? added section 2.0, typical performance curves , with characterization graphs. revision a (june 2011) ? original data sheet for the MCP3903 device.
MCP3903 ds25048b-page 52 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds25048b-page 53 MCP3903 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: MCP3903: six channel ? a/d converter * default option. contact microchip factory for other address options tape and reel: t = tape and reel temperature range: i = -40c to +85c e = -40c to +125c package: ss = small shrink output package (ssop-28) examples: a) MCP3903t-e/ss: tape and reel, six channel ? a/d converter, ssop-28 package b) MCP3903t-i/ss: tape and reel, six channel ? a/d converter, ssop-28 package part no. x temperature range device /xx package x tape and reel
MCP3903 ds25048b-page 54 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds25048b-page 55 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-402-6 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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